1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Background Art
Integrated circuits having MOS transistors are becoming more and more enhanced in terms of microminiaturization and operation speed. To prevent short-channeling effects such as punch-through along with the microminiaturization of MOS transistors, relatively shallow source and drain diffusion layers are formed.
To ensure high-speed operations of MOS transistors, the SALCIDE (Self-Aligned Silicide) technique is frequently used, as it reduces the contact resistance between the diffusion layers and a metal by forming a silicide layer on the diffusion layers in self-alignment. In the SALICIDE technique, silicide is formed by the interaction between the deposited metal and silicon as the substrate material. Therefore, in case a metal is directly deposited on shallow source and drain diffusion layers, silicide often appears after being downwardly thrust through the diffusion layers. As a result, leakage occurs between the source and drain diffusion layers and the substrate.
As a countermeasure, the Elevated Source-Drain technique has been developed. This is a technique that forms a silicide layer by depositing a metal on a silicon single-crystal layer selectively formed on the source and drain regions. Since the silicon of the silicon single-crystal layer interacts with the metal and forms the suicide, the silicide does not excessively erode the source or drain diffusion layers. Therefore, it was expected that the downward penetration of the silicide through the source or drain diffusion layer was prevented.
In the Elevated Source-Drain technique, silicon is epitaxially grown on the source and drain diffusion layers, which are limited regions of the entire surface of the semiconductor substrate. In order to obtain a sufficiently thick silicon single-crystal layer by the epitaxial growth process, the vapor-phase epitaxy (VPE) technique needs annealing at a high temperature not lower than 800° C.
Such high-temperature annealing, however, causes thermal diffusion of impurities in the source and drain diffusion layers. In the epitaxial growth process, excessive diffusion of these diffusion layers may invite the short-channeling effect in miniaturized MOS transistors. Therefore, high-temperature annealing of semiconductor substrates is not desirable after sources and drains are formed.
Apart from this, there is the Solid Phase Epitaxy (SPE) technique that first deposits amorphous silicon on a semiconductor substrate and thereafter anneals it at approximately 600° C. to change the silicon to single crystal. Even with the Solid Phase Epitaxy, a silicon single-crystal layer can be formed on source and drain diffusion layers. When annealing is carried out at a relatively low temperature around 600° C., thermal diffusion of source and drain diffusion layers is immaterial.
However, even in Solid Phase Epitaxy, if a silicon oxide exists on the semiconductor substrate, amorphous silicon deposited on the silicon oxide sometimes fails to change to single crystal. In this case, amorphous silicon on the source and drain diffusion layers can change to single crystal only partly and insufficiently for use in the Elevated Source-Drain technique. As a result, in a step of selectively etching the amorphous silicon deposited on the top surface of the semiconductor substrate, the silicon having failed to change to single crystal on source and drain regions is undesirably etched simultaneously. Therefore, this technique could not make the best use of the Elevated Source-Drain technique.
Especially when the semiconductor substrate is a p-type substrate containing an impurity such as boron, because it is easily oxidized, amorphous silicon deposited on the top surface of the p-type semiconductor substrate containing boron, or the like, is difficult to single-crystallize sufficiently.
These and other problems involved in the conventional techniques are discussed below with reference to the drawings.
FIGS. 20 through 24 are cross-sectional views that show a semiconductor substrate in an enlarged form to demonstrate a conventional method of manufacturing a semiconductor device in the order of its procedures.
As shown in FIG. 20, an isolating region 30 is formed in the semiconductor substrate 10. The substrate 10 has formed a gate insulating film 40 on its top surface and a gate electrode 60 on the gate insulating film 40. A sidewall protective layer 85 is formed on the sidewall of the gate electrode. The semiconductor substrate 10 further includes diffusion layers 70, 72 as source and drain layers.
The top surface of the semiconductor substrate 10 in the regions of the diffusion layers 70, 72 are exposed to epitaxially grow a silicon single-crystal layer thereon. However, the top surface of the semiconductor substrate 10 is oxidized when contacting air, and a silicon oxide 90 is produced on the top surface of the semiconductor substrate.
As shown in FIG. 21, an amorphous silicon layer 100 is deposited on the top surface of the semiconductor substrate and on the gate electrode 60.
As shown in FIG. 22, the amorphous silicon layer 100 is annealed. However, the silicon oxide 90 exists between the top surface of the semiconductor substrate 10 and the amorphous silicon layer 100, and locally prevents the amorphous silicon layer 90 from direct contact with the top surface of the semiconductor substrate 10. Since the amorphous silicon layer 100 can epitaxially grow only along the crystal on the top surface of the semiconductor substrate 10, part of the amorphous silicon layer 100 not contacting the top surface of the semiconductor substrate 10 cannot grow epitaxially even when it is annealed. As a result, the silicon single-crystal layer 120 transformed from the amorphous silicon layer 100 by annealing does not become uniform in thickness and quality on the top surface of the semiconductor substrate 10.
As shown in FIG. 23, as a result of etching by making use of the difference in etching rate between the silicon single-crystal layer and the amorphous or polycrystalline silicon, the amorphous silicon 100 and the polycrystalline silicon transformed from the amorphous silicon 100 are etched, and the silicon single-crystal layer 120 remains.
As shown in FIG. 24, a metal acts on the silicon deposited on the semiconductor substrate 10, as a result, a silicide layer 130 is formed. In regions where the silicon single-crystal layer 120 is thin, the deposited metal acts not only on the silicon of the silicon single-crystal layer 120 but also on the silicon of the diffusion layers 70, 72. Therefore, the diffusion layers 70, 72 are excessively encroached by the silicide layer 130, which may grow even beyond the diffusion layers 70, 72. Thus, the advantage of the Elevated Source-Drain technique is not harnessed sufficiently.
Here is needed a semiconductor device manufacturing method capable of forming a silicon single-crystal layer acceptable for use with the Elevated Source-Drain technique on source and drain diffusion layers at a relatively low temperature.
Additionally needed is a semiconductor device having a silicide layer formed by the Elevated Source-Drain technique and uniform in thickness and quality, keeping the contact resistance low between the source and drain diffusion layers on one part and source and drain electrodes on the other part, and available for more progressed microminiaturization than a conventional one.